Through Silicon Vias (TSVs) are an essential structure for 3D integration. TSVs enable vertical interconnects between chips or to a packaging substrate. Often, the ideal point to introduce the TSVs in the CMOS fabrication sequence is in the BEOL (back end of the line). The process used for creating TSVs then must etch through existing BEOL, MOL, and FEOL dielectrics that are already built on the wafer at the point of TSV introduction, and then continue the etch through the Si substrate until the desired depth of via has been attained, which typically corresponds to the final thickness of the substrate.
The requirement to etch through multiple BEOL dielectrics (which can reach a total thickness of 1 to 10 microns depending on where the TSVs are introduced) while leaving sufficient photoresist to mask the deep Si etch is very challenging. One option is to increase the thickness of the photoresist. But since the selectivity of many dielectrics in a typical dielectric etch is 1:1 to 2:1, the photoresist layer has to have a similar thickness to the dielectric being etched, e.g. 1 to 10 microns thick. New photoresist materials and tooling can be required, and lithography becomes more challenging as the thick resist limits the ability to print small features. Furthermore, the edge of the wafer must be protected by a ceramic ring during the etch (to prevent etching of the bevel). Any resist that extends under this ring must be removed after processing, which becomes more difficult as the resist is made thicker. Another option is to deposit a hardmask (e.g. silicon nitride, oxide, TiN, Al) as well as a photoresist layer. This complicates the integration as the hardmask must be deposited and patterned. Furthermore, the etch chemistry is typically chosen to have fast etch rates through the variety of dielectric films that are encountered in the back end of line, which makes it difficult to find a material with sufficient resistance to the etch to act as a suitable hardmask.
The drive to higher performance chips having greater density, energy efficiency, speed, etc. will require 3D integration, so there is a need to form TSVs by a method that minimizes consumption of materials and processing steps and requires little modification to current chip manufacturing lines.